Seven segment display, VHDL
BCD-to-seven-segment decoder written in VHDL, recovered from the original report.
- vhdl
- digital logic
- fpga
Problem
Learn FPGA design flow and VHDL by building something small and verifiable: a circuit that decodes a 4-bit BCD input into the correct seven-segment display pattern.
Approach
A combinational case statement maps each of the ten valid BCD values to its seven-bit segment pattern for a common-cathode display. A testbench steps the input through all ten digits in simulation, holding each for 100ns.
Result
Simulated correctly against the expected truth table for all ten digits in Vivado.
A note on this write-up
The original project files didn't survive. What's published here was recovered by transcribing the VHDL and testbench code directly from the written report, which included both in full. It's the real code, not a guess at what it might have looked like, just recovered from an unusual place.
What I'd do differently
Combinational-only, no multiplexing for multi-digit displays and no real handling of invalid input beyond a blank pattern. A next version would add multi-digit support and a clock-driven refresh scheme.